In modern integrated circuits (ICs), such as in battery-operated mobile or contactless systems, such as mobile phones etc., there typically are modes of operation (standby or sleep mode) in which the integrated circuit is to consume as little energy as possible while maintaining minimum functionality. Here, typically no computation operations or other signal exchanges take place whatsoever within an IC, and the entire IC is only allowed to have a preset, minimum energy turnover, which is typically also fixed by specific norms. With increasing miniaturization, i.e. the advance toward nanometer technologies, this becomes more and more difficult because the number of the circuit elements, i.e. the potential causes of leakage currents, increases per individual IC on the one hand, and the transistor leakage currents rise considerably by the miniaturization on the other hand, which is routed in the physical properties of the materials used and is caused by the small structural size, in particular. The problem of the high transistor leakage currents particularly exists for modern “deep sub-micron” technologies, in which transistor channel lengths in the range of 100 nm and below, as well as gate oxide thicknesses of 2.5 nm and below are used. The transistor leakage current thus is that current consumed by a transistor when operated statically, i.e. does not change its state by switching, wherein the typical switching losses occur. The increasing miniaturization thus leads to increased current consumption already in an inactive state of a circuit, i.e. when no computation operations are performed in the circuit.
In the conventional art, there is a series of different approaches to reduce the energy consumption of ICs or processors in a so-called sleep mode, in which the ICs are completely or partially switched off, i.e. disconnected from supply voltage. In general, those parts of the IC the electric function of which is needed again only when the entire system leaves the sleep mode and resumes its normal mode of operation can be switched off. Examples for parts of an IC that can be switched off, for example, are subunits for the generation of control signals, the storing elements of which are allowed to loose their information in the sleep mode, since they may be automatically set (reset) to a certain initial state ensuring their function before resuming the normal operation. As an alternative to switching off, the supply voltage of such parts of the IC may be lowered considerably, so that memory elements still retain their information, for example, but it is no longer possible to perform switching operations, i.e. to switch transistors over (which also is not necessary in the sleep mode).
But there is a series of sub-circuits, for example of a CPU (central processing unit) of a system, the switch-off of which would entail a loss of information preventing operation of the system after ending the sleep mode. In addition, it is to be evaluated whether energy or time loss, which may be accompanied by switching off sub-circuits, is acceptable when ending the sleep mode and can thus be justified by the energy saved during the sleep mode. Parts of an IC or a CPU that typically cannot be switched off, i.e. the information of which also has to be maintained in the sleep mode, for example, are memory macros, such as SRAMs, caches and processor registers (register files) as well as parts of data paths (access memory addresses etc.). When switching off the active calculating unit of a CPU, this information has to be maintained, because the CPU strictly needs this information when ending the sleep mode (upon wake-up) to be able to resume the operation at the point at which the sleep mode was initiated. Overall, data that has to be maintained usually is instructions and data for the CPU, as well as intermediate results of the computations of the CPU and state registers.
Such information is usually stored in SRAM-based sub-circuits of the IC or the CPU, i.e. using memory technologies that maintain the content of a stored value themselves when the supply voltage is available, i.e. that do not always have to be refreshed again, like DRAM memories.
Such SRAM regions therefore must not be disconnected from the supply voltage and hence are to be electrically insulated, in the sleep mode, from those units that are disconnected from the supply voltage or the supply voltage of which is lowered.
The energy consumption of an IC in the sleep mode is typically dominated by the leakage currents of SRAM macros or SRAM cells or by circuit blocks, such as caches or register files based on SRAM technologies.
The principle construction of a typical SRAM cell is shown in FIG. 6.
The memory access to an SRAM cell here is done via a bit line pair of a first bit line 2a and a second bit line 2b. An SRAM cell 4 is formed by two inverters 6a and 6b, wherein the output of the inverter 6a is connected to the input of the inverter 6b, and wherein the output of the inverter 6b is connected to the input of the inverter 6a, as it can be seen in FIG. 6. A memory content, once impressed in the cell at circuit nodes 8a (b) and 8b (bq), thus is automatically maintained by the inverters 6a and 6b connected as described above. The inverters 6a and 6b are typically constructed by means of suitably connected NMOS and PMOS transistors, which also have to be supplied with a supply voltage. Here, the upper supply potential is typically referred to as VDD and the lower supply potential (ground) as VSS. Since the exact realization of the inverters as well as the external connection of the inverters by means of supply voltages is not relevant for the principle functioning of an SRAM cell, these two aspects of an SRAM cell are not illustrated in FIG. 6.
During the normal operation, i.e. when a value is stored in the SRAM cell, the circuit nodes 8a and 8b are at defined potentials, wherein different potentials each, namely VDD or VSS, are present at the circuit nodes 8a and 8b according to the connection of the inverters 6a and 6b. For example, if the circuit node 8a is at the potential VDD, the circuit node 8b is at the potential VSS. Moreover, in order to be able to change the memory content of the SRAM cell 4, the circuit node 8a is connected to the bit line 2a via a first NMOS transistor 10a in electrically conductive manner, and the second circuit node 8b can be connected to the bit line 2b via a second NMOS transistor 10b. The gate terminals of the transistors 10a and 10b are connected to a word line 12, so that, when applying a switch signal to the word line 12, the transistors 10a and 10b are switched to the conducting state, and the first circuit node 8a thus is connected to the bit line 2a, and the second circuit node 8b to the bit line 2b. 
When writing content into the SRAM cell, at first the bit line 2a and the bit line 2b are brought to potentials corresponding to the bit value to be stored (for example VDD on the bit line 2a and VSS on the bit line 2b). Ensuing selecting of the SRAM cell 4 by applying a switching voltage to the word line 12 then writes the bit value into the memory cell 4 by bringing the first circuit node 8a to the potential of the first bit line 2a and the second circuit node 8b to the potential of the bit line 2b by making the conducting connection.
The process of reading substantially works in equivalent manner, but a so-called precharge is to be performed first to enable reading, i.e. the potentials of the bit lines 2a and 2b are to be brought to VDD, so that in the ensuing selection of the word line the potential of that bit line can be drawn to VSS, which is connected to the circuit node that is at VSS.
One possibility for the reduction of the loss power of an SRAM-based subcircuit may be to lower the supply voltage of the subcircuit, in order to reduce the leakage current of the individual transistors. Such lowering should, however, not become so large that the system of two inverters 6a and 6b can no longer maintain the memory state. Hence, the possibility of lowering the supply voltage is limited, so that the energy saving that can be attained is also limited.
The mechanisms leading to the spurious leakage currents of individual transistors or SRAM cells are being examined intensively. For example, in “Ultralow-power SRAM technology” (R. W. Mann et al., IBM J. RES. & DEV., volume 47, no. 5/6, September/November 2003), the mechanisms leading to the occurrence of leakage currents are described in detail. The so-called gate leakage, the diffusion leakage, the subthreshold leakage and the so-called gate-induced drain leakage (GIDL) have important shares in the overall loss power. In the momentary stage of the technological development, the subthreshold leakage and the GIDL, in particular, are relevant here, but the contribution of the gate leakage will be more and more important in the future with the further structural shrinkage to be expected (with “very deep sub-micron” technologies with channel lengths of clearly below 100 nm and gate oxide thicknesses below 2 nm).
The subthreshold leakage describes the flow of current arising through the transistors, when different electrical potentials are present at the source and drain terminals, even if a potential lying far below the actual switching voltage (threshold voltage Vt) is present at the gate terminal. The subthreshold leakage is strongly temperature dependent and therefore typically the dominant leakage current mechanism at higher temperatures.
The gate-induced drain leakage GIDL contributes to the leakage current in the geometric regions in which the gate region geometrically overlaps with the source region and/or the drain region within the transistor. The gate-induced drain leakage is caused by band-to-band tunneling of charge carriers (electrons) in the above-described overlapping regions. The band-to-band tunneling effect is enhanced if additional energy levels for the charge carrier become possible between the band due to contaminations and/or process fluctuations in the overlapping regions, because the leakage current is then additionally increased by the so-called trap-assisted band-to-band tunneling.
As described in the foregoing, an SRAM cell typically consists of six individual transistors, wherein a measure for the reduction of the SRAM leakage currents known in the conventional art consists in supplying the source terminals of the n-channel transistors of the six-transistor SRAM cells not with VSS (ground) in the sleep mode, but with a so-called “virtual VSS”, i.e. a potential vVSS lying at about 0.5 V above VSS, while the p substrate of the n-channel transistors still remains connected to VSS. For example, this may be realized by VSS being shorted to vVSS via a conducting n-channel transistor in the normal operation (the control signal at the gate of this transistor is connected to VDD). In the sleep mode, however, the n-channel transistor mentioned is made non-conducting (the control signal at the gate of this transistor is connected to VSS). Via a further n-channel transistor that is connected as a diode and the drain and gate of which are connected to vVSS and the source of which to VSS, now vVSS may rise up to about a starting voltage Vth above VSS (through leakage currents).
By this measure, however, substantially only the subthreshold current (subthreshold leakage) of n-channel transistors is reduced, because the starting voltage Vth of these transistors is increased through the so-called substrate control effect, and because the subthreshold voltage depends on Vth exponentially. But because the subthreshold current is strongly temperature dependent, as described above, this measure for lowering the current consumption of SRAM cells is only suited conditionally in standby, in which typically only low thermal loss power is generated, i.e. the ambient temperature is low.
In these cases, in which the gate-induced drain leakage has a relevant share of the overall leakage current for present technologies, the current consumption is positively influenced only in parts by this measure. The gate-induced drain leakage has a multiplicity of mechanisms contributing to the GIDL, such as the above-mentioned trap-assisted band-to-band tunneling effect. This, as well as other shares of the GIDL, have exponential dependence on the difference of the potentials at gate and drain/source or substrate of the respective transistor.